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| HD74BC245A Octal Bus Transceivers With 3 State Outputs REJ03D0282-0400Z (Previous ADE-205-008B (Z)) Rev.4.00 Jul.16.2004 Description The HD74BC245A provides high drivability and operation equal to or better than high speed bipolar standard logic IC by using Bi-CMOS process. The device features low power dissipation that is about 1/5 of high speed bipolar logic IC, when the frequency is 10 MHz. The device has ten buffers with three state outputs in a 20 pin package. Each device has an active low enable input G and a direction control input DiR. When DiR is high, data flows from the A inputs to the B outputs. When DiR is low, data flows from the B inputs to the A outputs. When G is high, disables both A and B ports by placing then in a high impedance. Features * Input/Output are at high impedance state when power supply is off. * Built in input pull up circuit can make input pins be open, when not used. * TTL level input * Wide operating temperature range Ta = -40 to + 85C * Ordering Information Part Name HD74BC245AP HD74BC245AFPEL HD74BC245ATELL Package Type DILP-20 pin TSSOP-20 pin Package Code DP-20N, -20NEV TTP-20DAV P FP T Package Abbreviation -- EL (2,000 pcs/reel) ELL (2,000 pcs/reel) Taping Abbreviation (Quantity) SOP-20 pin (JEITA) FP-20DAV Note: Please consults the sales office for the above package availability. Function Table Control Inputs G L L H H: L: Z: High level Low level High impedance L H X DiR B data to A bus A data to B bus Z Operation Rev.4.00, Jul.16.2004, page 1 of 8 HD74BC245A Pin Arrangement DiR A1 A2 A3 A4 A5 A6 A7 A8 GND 1 2 3 4 5 6 7 8 9 10 (Top view) 20 19 18 17 16 15 14 13 12 11 VCC G B1 B2 B3 B4 B5 B6 B7 B8 Absolute Maximum Ratings Item Supply voltage Input diode current Input voltage Output voltage VCC IIK VIN VOUT Symbol Rating -0.5 to +7.0 30 -0.5 to +7.5 -0.5 to +7.5 V mA V V Unit Off state output voltage VOUT(off) -0.5 to +5.5 V Storage temperature Tstg -65 to +150 C Note: 1. The absolute maximum ratings are values which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. Recommended Operating Conditions Item Supply voltage Input voltage Output voltage Operating temperature VCC VIN VOUT Topr Symbol 4.5 0 0 -40 Min 5.0 -- -- -- Typ 5.5 VCC VCC 85 8 Max V V V C ns/V Unit Input rise/fall time*1 tr, tf 0 -- Note: 1. This item guarantees maximum limit when one input switches. Waveform: Refer to test circuit of switching characteristics. Rev.4.00, Jul.16.2004, page 2 of 8 HD74BC245A Logic Diagram DiR G B1 B2 B3 B4 B5 B6 B7 B8 A1 A2 A3 A4 A5 A6 A7 A8 Rev.4.00, Jul.16.2004, page 3 of 8 HD74BC245A Electrical Characteristics (Ta = -40C to +85C) Item Input voltage Output voltage Symbol VIH VIL VOH VOL Input diode voltage Input current VIK II 4.5 4.5 4.5 4.5 4.5 5.5 5.5 5.5 Short circuit output current*1 Off state output current Supply current IOS IOZH IOZL ICCL ICCH ICCZ ICCT*2 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 VCC(V) Min 2.0 -- 2.4 2.0 -- -- -- -- -- -- -- -100 -- -- -- -- -- -- Max -- 0.8 -- -- 0.5 0.55 -1.2 -250 100 1.0 100 -225 -100 -250 31.5 0.5 4.5 1.5 V V V V V V V A A A A mA A A mA mA mA mA IOH = -3 mA IOH = -15 mA IOL = 48 mA IOL = 64 mA IIN = -18 mA VIN = 0 V An or Bn, VIN = 5.5 V DiR or G, VIN = 5.5 V DiR or G, VIN = 7.0 V VO = 0 V, VIN = 5.5 V VO = 2.7 V VO = 0.5 V VIN = 0 or 5.5 V All outputs is "L" VIN = 0 or 5.5 V All outputs is "H" VIN = 0 or 5.5 V All outputs is "Z" VIN = 3.4 or 0.5 V Unit Test Conditions Notes : 1. Not more than one output should be shorted at a time and duration of the short circuit should not exceed one second. 2. When input by the TTL level, it shows ICC increase at per one input pin. Switching Test Method (CL = 50 pF) Ta = 25C VCC = 5.0 V Min Max 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0(Typ) 15.0(Typ) 6.0 6.0 6.0 6.0 9.0 9.0 9.0 9.0 8.0 8.0 8.0 8.0 Ta = -40 to 85C VCC = 5.0 V 10% Min Max 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 -- -- 7.0 7.0 7.0 7.0 11.0 11.0 11.0 11.0 10.0 10.0 10.0 10.0 Item Propagation delay time Symbol tPLH tPHL tPLH tPHL Unit ns ns ns ns ns ns pF pF Test Conditions An to Bn Bn to An G to Bn G to An G to Bn G to An VIN = VCC or GND VI/O = VCC or GND Output enable time tZH tZL tZH tZL Output disable time tHZ tLZ tHZ tLZ Input capacitanse Input/output capacitance CIN CI/O Rev.4.00, Jul.16.2004, page 4 of 8 HD74BC245A Test Circuit VCC G Output VCC See Function Table Input Pulse Generator Zout = 50 A1 B1 DiR S1 500 CL= 50 pF 450 50 Scope *4 OPEN 7V Notes: 1. 2. 3. 4. CL includes probe and jig capacitance. A2-B2, A3-B3, A4-B4, A5-B5, A6-B6, A7-B7, A8-B8 are identical to above load circuit. S1: Input-Output change switch. Open: tPLH, tPHL, tZH, tHZ 7 V: tZL, tLZ Rev.4.00, Jul.16.2004, page 5 of 8 HD74BC245A Waveforms-1 tr 90% Input 1.5 V 10% t PLH 90% 1.5 V 10% t PHL 1.5 V 1.5 V VOL 0V VOH Output tf 3V Waveforms-2 tf 90% 1.5 V 10% t ZL tr 90% 1.5 V 10% t LZ 3.5 V Waveform-A t ZH 1.5 V VOL + 0.3 V t HZ VOH - 0.3 V 1.5 V 0V VOL 3V G 0V VOH Waveform-B Notes: 1. tr = 2.5 ns, tf = 2.5 ns 2. Input waveform: PRR = 1 MHz, duty cycle 50% 3. Waveform-A shows input conditions such that the output is "L" level when enable by the output control. 4. Waveform-B shows input conditions such that the output is "H" level when enable by the output control. Rev.4.00, Jul.16.2004, page 6 of 8 HD74BC245A Package Dimensions As of January, 2003 Unit: mm 24.50 25.40 Max 20 11 1 0.89 1.27 Max 10 1.30 7.62 7.00 Max 2.54 Min 5.08 Max 0.51 Min 6.30 2.54 0.25 0.48 0.10 0.25 - 0.05 0 - 15 + 0.11 Package Code JEDEC JEITA Mass (reference value) DP-20N -- Conforms 1.26 g Unit: mm 24.50 25.40 Max 20 11 1 0.89 1.27 Max 10 1.30 7.62 7.00 Max 2.54 Min 5.08 Max 0.51 Min 6.30 2.54 0.25 *0.48 0.08 *0.25 0.06 0 - 15 *NI/Pd/AU Plating Package Code JEDEC JEITA Mass (reference value) DP-20NEV -- Conforms 1.26 g Rev.4.00, Jul.16.2004, page 7 of 8 HD74BC245A As of January, 2003 12.6 13 Max 20 Unit: mm 11 1 10 5.5 0.80 Max 2.20 Max *0.20 0.05 0.20 7.80 + 0.30 - 1.15 1.27 *0.40 0.06 0.10 0.10 0 - 8 0.70 0.20 0.15 0.12 M *Ni/Pd/Au plating Package Code JEDEC JEITA Mass (reference value) FP-20DAV -- Conforms 0.31 g As of January, 2003 Unit: mm 6.50 6.80 Max 20 11 4.40 1 10 0.65 1.0 6.40 0.20 0.65 Max *0.15 0.05 *0.20 0.05 0.13 M 1.10 Max 0.10 0.07 +0.03 -0.04 0 - 8 0.50 0.10 *Ni/Pd/Au plating Package Code JEDEC JEITA Mass (reference value) TTP-20DAV -- -- 0.07 g Rev.4.00, Jul.16.2004, page 8 of 8 Sales Strategic Planning Div. Keep safety first in your circuit designs! Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. 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